This invention relates to a semiconductor device and the method of manufacturing the semiconductor device.
The improvement in reliability of a gate oxide film in a MOS transistor where a silicon oxide film is employed as the gate oxide film is one of important factors in enhancing the performance of the MOS transistor. However, the thinning of the gate oxide film is considered to invite a problem of deteriorating the reliability of the gate film (e.g. the deterioration of TDDB, an increase in leak current, or the deterioration of dielectric strength) that may be brought about by a plasma damage at the occasion of introducing an impurity into a gate electrode or at the occasion of working a gate electrode, or by an ion damage at the occasion of implanting ions into a channel region and into a source/drain region.
There has been proposed, as one of the solutions to overcome the aforementioned problem, a method of forming a gate electrode using a dummy gate pattern (e.g. Japanese Patent Application H/8-356493). This method is featured in that a dummy gate pattern is formed via a pad oxide film at a predetermined gate region on a semiconductor substrate at first, and, after finishing the implantation of ions into a channel region and a source/drain region, the dummy gate pattern and the pad oxide film are removed to form a groove, in which a gate insulating film and a gate electrode are subsequently formed by means of.CMP. According to this method, it is possible to avoid the gate insulating film from being damaged, i.e. to obviate the aforementioned plasma damage at the occasion of working a gate electrode, or the aforementioned ion damage at the occasion of implanting ions into a channel region and into a source/drain region.
However, this method is accompanied with a problem that it is difficult to control the dimension of the gate electrode. Specifically, since the etching rate of an SiO.sub.2 film (interlayer insulating film) formed around the dummy gate pattern is higher than that of the pad oxide film (SiO.sub.2 thermal oxide film), the interlayer insulating film is caused to become thinner extremely at the occasion of removing the pad oxide film, thus resulting in a great change in width of the groove for forming a gate electrode therein.
As a countermeasure to cope with this problem, it is conceivable to form an SiN film on the side wall of the dummy gate pattern. FIG. 1 illustrates the construction of one example of a transistor provided on its side wall with such an SiN film. In FIG. 1, the reference numeral 101 denotes a gate electrode, the numeral 102 a gate insulating film, the numeral 103 a source/drain diffusion layer, the numeral 104 a side wall insulating film, and the numeral 105 a pad oxide film.
However, even if the side wall insulating film (SiN film) 104 is provided in this manner, the oxide film 105 formed below the side SiN film 104 is caused to set back (to become thinner) at the occasion of removing an exposed portion of the pad oxide film disposed below the dummy gate pattern, thereby forming a recessed portion 106 at the lower edge portion of the gate electrode 101. As a result, a dielectric strength between the source/drain region 103 and the gate electrode 101 may be deteriorated, or the film thickness of the gate insulating film 102 at the lower edge portion of the gate electrode 101 may be caused to change.
As a result, there will be raised a serious problem such as a deterioration in property (a reduction of channel current, an increase of interfacial level, etc.) or in reliability (a lowering of insulating property due to an electrostatic focusing at the lower edge portion of the gate electrode or due to a poor filling of gate insulating film) of a transistor. Furthermore, due to the formation of the recessed portion 106 at the lower edge portion of gate electrode, the bottom width of groove to be filled with a gate electrode may be caused to change, thus making it difficult to control the dimension of the gate electrode also in this case.
As explained above, a method comprising the steps forming a pad oxide film (a dummy insulating film) and a dummy gate pattern in a predetermined gate region, removing the dummy gate pattern and the dummy insulating film thereby forming a groove, and then forming a gate insulating film and a gate electrode in the groove is accompanied with a problem that the controlling of dimension of the groove, i.e. the controlling of dimension of the gate electrode is difficult.
Further, a method of forming an SiN film on the side wall of a dummy gate pattern is also accompanied with a problem as mentioned above that a dummy insulating film is laterally etched at the occasion of removing an exposed portion of the dummy insulating film, thus forming a recessed portion at the lower edge portion of the gate electrode whereby raising problems of deteriorating the performance and reliability of the resultant transistor. Additionally, due to the generation of this recessed portion, the controlling of dimension of gate electrode also becomes difficult.
On the other hand, with a view to enhance the performance of a semiconductor integrated circuit using an MIS type transistor, there has been tried to reduce the film thickness of an effective gate insulating film by employing at least partially a low resistance metallic material for the gate electrode, or by employing at least partially a ferroelectric film such as Ta.sub.2 O.sub.5 for the gate insulating film. In this case, for the purpose of avoiding a deterioration of the properties of gate electrode/gate insulating film at the occasion of a high temperature processing such as the activation of source/drain region, a method has been proposed wherein the source/gate drain regions are formed in advance and then a groove is formed in self-alignment at a predetermined gate-forming region in relative to the source/drain, a gate insulating film and a gate electrode being subsequently buried in the groove as mentioned above.
Next, a typical example of the manufacturing process of a semiconductor device according to the prior art will be explained with reference to FIGS. 2A to 2J.
As shown in FIG. 2A, an SiO.sub.2 film 112 having a thickness of 5 nm is formed on the surface of a predetermined transistor-forming region of a Si substrate 111 provided with a trench type element isolation layer (not shown). Then, a poly-Si film 113 having a film thickness of 300 nm for forming a dummy gate pattern is deposited on this SiO.sub.2 film 112.
Then, as shown in FIG. 2B, the poly-Si film 113 is worked into a dummy gate pattern by means of lithography and RIE for instance. Subsequently, as shown in FIG. 2C, an ion-implantation of phosphorus ion is performed for instance at a dosage of 4.times.10.sup.13 cm.sup.-2 using the dummy gate pattern 113 as a mask to form n-type source/drain regions 114.
After an Si.sub.3 N.sub.4 film is deposited all over the upper surface of the resultant substrate, an overall etch-back is performed thereby to form an Si.sub.3 N.sub.4 side wall 115 on the side wall of the dummy gate pattern 113. Thereafter, an ion-implantation of arsenic ion is performed for instance at a dosage of 5.times.10.sup.15 cm.sup.-2 to form n+ type source/drain regions 116 thereby forming an LDD structure as shown in FIG. 2D. Subsequently, an annealing is performed for 30 seconds at a temperature of 1,000.degree. C. to activate the source/drain regions.
Thereafter, as shown in FIG. 2E, a CVD-SiO.sub.2 film 117 is deposited entirely to a thickness of 300 nm for instance, and then densified over a period of 30 minutes in a N2 gas atmosphere at a temperature of 800.degree. C. for instance. Then, the upper surface of the resultant substrate is flattened by entirely performing a chemical and mechanical abrasion, whereby allowing the upper surface of the dummy gate pattern 113 to expose. Then, as shown in FIG. 2F, the exposed dummy gate pattern 113 is selectively removed, and the SiO.sub.2 film 112 disposed below the dummy gate pattern 113 is also removed thereby to form a groove 118 for forming a gate insulating film and a gate electrode.
After a Ta.sub.2 O.sub.5 film 119 is entirely deposited to a thickness of 20 nm as a gate insulating film, a Ru film 120 is entirely deposited to a thickness of 300 nm as a gate electrode, and the resultant upper surface is entirely abraded by chemical and mechanical means, thereby forming a transistor structure as shown in FIG. 2G wherein the gate insulating film 119 and the gate electrode 120 are buried in the groove 118. Thereafter, though not shown, ordinary procedures such as the deposition of insulating interlayer film, the formation of contact holes in the interlayer film and the formation of wiring through the contact holes are performed.
However, as mentioned above, the SiO.sub.2 film 112 is laterally etched at the occasion of removing an exposed portion of the SiO.sub.2 film 112 as shown as an enlarged view in FIG. 2H, thereby forming a laterally recessed portion 121 in the groove 118 for housing the gate electrode and the gate insulating film therein. As a result, when the gate insulating film 119 and the gate electrode 120 are successively formed in the groove 118, a hollow portion 122, i.e. a defective filling of gate electrode 120 is caused to generate as shown in FIG. 2I, or the radius of curvature of the lower corner portion 123 of the gate electrode 120 is caused to reduce as shown in FIG. 2J.
As a result, a transistor to be obtained would be poor in dielectric strength at the gate edge portion of the gate insulating film, i.e. poor in reliability.